While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

Axis Systems has developed an emulation and verification tool specifically aimed at users of intellectual property. RCC Model Compiler can link together pre-compiled blocks of RTL code. This allows ...

“Golden” RTL code has been seen as a holy grail of IC design for many years. It promises to deliver code that is reusable in future designs. However, golden RTL is very difficult to achieve. Too many ...

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, ...

Achieves up to 75 percent power savings in critical semiconductor blocks; significantly reduces development costs and design risk OLDENBURG, Germany and SAN JOSE, Calif. -- May 15, 2007 -- ChipVision ...

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for ...