To test complex devices, test engineers must rely on the vector sets generated by verification engineers. Unfortunately, verification engineers—who work in a software simulation environment—often have ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief ...

There are many ways to categorize engineers—to “slice and dice” them, if you will. I’m speaking figuratively, of course (we don’t want anyone to get any unfortunate ideas…especially since… the ...

BENGALURU, India — Two engineers at Oski Technology Inc. (Fremont, Calif.) have demonstrated a formal verification planning process and associated verification strategy that they say is a ...

The pandemic accelerated the sharp rise in professionals working from home. Some people did well while others struggled. This dynamic was particularly acute in the semiconductor industry, which has ...

Today, project teams build huge verification environments, where verification consumes 40-70% of the resources needed in a typical cycle. Because a verification environment typically contains ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...