Semiconductor Engineering

SVT (Six Stacked Vertical Transistors) SRAM Cell Architecture Introduction: Design And Process Challenges Assessment

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual ...
Electronic Design

Crolles2 Alliance reveals ultra-dense SRAM cell in 45 nm conventional bulk CMOS

The Crolles2 Alliance, which includes Freescale Semiconductor, Philips and STMicroelectronics, has created six-transistor SRAM-bit cells with an area of less than 0.25 square microns, or about half ...
EDN

Low Power SRAM Design [Cadence ICFB, Synopsys DC, 0.12μmCMOS, Hspice]

Designed an 8-Kbit SRAM using sleep transistors to reduce power dissipation. 130nm technology is used to design SRAM cells and HSPICE simulations are used to determine the optimal number and sizes of ...
TechRepublic

Design and Verification of Low Power SRAM Using 8T SRAM Cell Approach

SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high ...
Electronic Design

Alliance Produces Ultra-Dense SRAM Cell In 45nm CMOS Technology

The Crolles2 Alliance has described at the VLSI Symposium in Kyoto, Japan, the creation, under production conditions, of six-transistor SRAM-bit cells with an area less than 0.25 square microns?half ...