EDN

Assess Power-Supply Noise Rejection in Low-Jitter PLL Clock Generators

This article discusses the effects of power-supply noise interference on PLL-based clock generators, and describes several measurement techniques for evaluating the resulting deterministic jitter (DJ) ...
EDN

SIGNAL CHAIN BASICS #61: Clock jitter demystified-random jitter and phase noise, Part 2

Editor's note: Signal Chain Basics is an ongoing and popular series; click here for a complete, linked list of all installments.) In Signal Chain Basics Part 56 we discussed the fundamental ...