Serial Cables Introduces High-Performance Dual EDSFF PCIe 6.0 Adapter for Next-Gen CXL Memory Workloads

Scale memory capacity in the enterprise with dual x8 EDSFF interfaces for CXL architectures, designed for flexibility ...
HPCwire

Why Memory Pool Architectures Will Redefine KV Cache for AI Inference

The conversation surrounding AI infrastructure has correctly identified the key value (KV) cache as a critical bottleneck in scaling AI inference. As models push toward longer context windows and ...
techinsights

Samsung and SK hynix Are Racing to Build Memory You Can Share, Not Just Store

At OCP 2026, Samsung and SK hynix both detailed strategies for addressing the memory demands of agentic AI’s key-value cache workloads, with coverage framing the announcements as further evidence that ...
VentureBeat

Google's new neural-net LLM architecture separates memory components to control exploding costs of capacity and compute

A new neural-network architecture developed by researchers at Google might solve one of the great challenges for large language models (LLMs): extending their memory at inference time without ...
Yahoo Finance

High Bandwidth Memory Market to Surpass US$ 5.81 Billion by 2033 Driven by AI Accelerators and Advanced 3D-Stacked Memory Architectures | Astute Analytica

Chicago, Feb. 09, 2026 (GLOBE NEWSWIRE) -- According to recent data from Astute Analytica, the global high bandwidth memory market is poised for significant growth, with revenues expected to rise from ...
Semiconductor Engineering

AI Memory: Enabling The Next Era Of High-Performance Computing

The rapid advancement of artificial intelligence (AI) is driving unprecedented demand for high-performance memory solutions. AI-driven applications are fueling significant year-over-year growth in ...
Yahoo Finance

Compute-In-Memory APU Achieves GPU-Class AI Performance at a Fraction of the Energy Cost

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Business Wire

Primemas Shatters AI Memory Wall at FMS 2026 with CXL Full-Stack Products and Micron Collaboration on the Abaco Project

SANTA CLARA, Calif.--(BUSINESS WIRE)--Primemas Inc., a pioneer in next-generation AI memory system architectures and chiplet-based silicon, showcased its latest CXL memory innovations at the Future of ...
Semiconductor Engineering

Accelerator Architecture For In-Memory Computation of CNN Inferences Using Racetrack Memory

A new technical paper titled “Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems” was published by researchers at National ...
Nature

Spintronic Memory Architectures for Energy-Efficient Computing

Spintronic memory architectures exploit the intrinsic spin of electrons, alongside their charge, to store and process information in magnetic materials. By integrating magnetic tunnel junctions (MTJs) ...
NextBigFuture

NEO Semiconductor X-HBM Will Have 16X Bandwidth and 10X Memory Density

Neo Semiconductor X-HBM architecture will deliver 32K-bit wide data bus and potentially 512 Gbit per die density. It offering 16X more bandwidth or 10X higher density than traditional HBM. NEO ...
Nature

Spintronic Memory Architectures for Energy-Efficient Computing articles from across Nature Portfolio

In-memory computing (IMC) is a paradigm that enables neural network inference by computing analog matrix-vector multiplications (MVM) directly in memory crossbar arrays, with the potential for energy ...